#include "ustc_comdef.h"
#include "ustc_custom.h"
#include "ustc_hif.h"
#include "ustc_api.h"
#include "ramdisk.h"

extern SD_PARA_T *gp_para_sd;
extern void ustc_sdc_init_card(void);
extern USTC_U32 VectorTable[];

extern void __irq ISR_S3C44B0(void);

USTC_U32 udisk_size=15*1024*1024;
#if (S3C44B0_TEST_PLATFORM>0)
USTC_U32	 ramdisk_addr=0x0C018000;//S3C44B0
USTC_U32	*usb_cache=(USTC_U32*)0x0C008000;
#else
USTC_U32	 ramdisk_addr=0x01000000;//CUST
USTC_U32	*usb_cache=(USTC_U32*)0x1000000;
#endif

#ifndef _TEST_PATTERN_
extern SD_PARA_T para_sd;
int test_usb()
#else
SD_PARA_T para_sd;
int c_main()
#endif
{
	USTC_U32 diskID=0;
	USTC_DISK_T disk;
	USTC_U8 vendor[]="RSRGroup";
	USTC_U8 product[]="UDisk";

//	s3c44bx_init();
	
	ustc_tp_init();
	
	ustc_outh(HIF_PLL_CFG, 0x2F0C);

	ustc_delay(100000);

	ustc_outh(HIF_SYS_CLK_EN, HIF_CLK_EN_SD|HIF_CLK_EN_SD_RAM|HIF_CLK_EN_USB|HIF_CLK_EN_USB_PHY);

	ustc_sw_reset_exit(0xFFFF);
	
	ustc_udisk_init(usb_cache, vendor, product);
	

#if 0//(S3C44B0_TEST_PLATFORM>0)
//mount RAM Disk
	ramdisk_init((USTC_U32*)ramdisk_addr, udisk_size);

	disk.block_cnt=udisk_size/512;
	disk.read=ramdisk_read;
	disk.write=ramdisk_write;

	ustc_udisk_mount(&disk);
#endif

	if (1) do
	{
		ustc_sdc_init_card();

		if (gp_para_sd->sd_block_number)
		{
			disk.block_cnt=gp_para_sd->sd_block_number;
			disk.read=ustc_sdc_read;
			disk.write=ustc_sdc_write;
			ustc_udisk_mount(&disk);
		}
	}while (0);



	//reset USB
	ustc_sw_reset(HIF_RST_USB,0);

#if (S3C44B0_TEST_PLATFORM>0)
	VectorTable[13]=(USTC_U32)ISR_S3C44B0;
#else
	VectorTable[13]=(USTC_U32)ustc_udisk_isr;
#endif

	ustc_int_disable(0xFFFF);
	ustc_int_enable(HIF_INT_STA_USB);

	ustc_udisk_start();

	enable_irq(0);
		
	while (1)
	{
//		if (ustc_udisk_isr())
//			ustc_udisk_isr();
			ustc_udisk_process();
	}
}

void ustc_sdc_init_card()
{
	gp_para_sd=&para_sd;

	gp_para_sd->sd_cmd_timeout=0x100000;
	gp_para_sd->sd_timeout=0x100000;
	gp_para_sd->sd_line_mode = 1;
	gp_para_sd->ustc_sdc_init_delay1=0x8000;
	gp_para_sd->ustc_sdc_init_delay2=0x8000;
	gp_para_sd->sd_index = 0;
	gp_para_sd->sd_clk_div = 0x300;
	gp_para_sd->sd_clk_phase_cfg = 1;

	ustc_sw_reset(HIF_RST_SD|HIF_RST_SD_REG, 0);
	
	ustc_sdc_init(gp_para_sd);
}

void __irq ISR_S3C44B0(void)
{
	ustc_udisk_isr();

	*(unsigned long*)0x1E00024=0x200000;//clear EINT4 pendding
	*(unsigned long*)0x1D20054=1;//clear EINT4 pending
}

